#include <config.h>
#include <arch/arm.h>
#include <arch/cpu/soc/mach/setup.h>

.global _start
_start:
	b reset_handler
	b undef_handler
	b swi_handler
	b iabort_handler
	b dabort_handler
	b hang
	b irq_handler
	b fiq_handler

    /* set the cpu to SVC32 mode and disable IRQ FIQ */
    msr cpsr_c, #(ARM_MODE_SVC | ARM_INT_MASK)

	MACHINE_SETUP

clear_bss:
	ldr r0, =__bss_start
	ldr r1, =__bss_end
	mov r2, #0
clbss_l:
	cmp r0, r1
	strne r2, [r0]
	addne r0, r0, #4
	bne clbss_l
	
	/* set sp */

	/* kernel_start */

undef_handler:
swi_handler:
iabort_handler:
dabort_handler:
irq_handler:
fiq_handler:

vector_irq:
	sub lr, lr, #4

	/* save parent pc and parent cpsr */
    stmfd sp!, {lr}
	mrs lr, spsr
	stmia sp!, {lr}

    mrs lr, cpsr
	bic lr, #ARM_MODE_MASK
	orr lr, lr, #ARM_MODE_SVC
    msr spsr_c, lr

	sub sp, sp, #(FRAME_SIZE - 4)
	stmia sp, {r1 - r12}
	ldmia r0, {r3 - r5}
	add r7, sp, #S_SP - 4
	svc_handler


